Ferroelectric materials based non-volatile memory (NVM) devices are being investigated for ferroelectric random access memory (FeRAM) applications due to their unlimited write cycles, high speed, longer life times, high integration density and low power consumption compared with the flash and conventional dynamic random access memory (DRAM)1,2,3,4. Ferroelectric materials are spontaneously polarized and can store information on the basis of their remnant polarization, i.e., polarization remains in the material even in the absence of electric field. Therefore, it has a great potential for use in NVM devices. Monolithic integration of ferroelectric materials on silicon (Si) opens up a new pathway towards developing advanced Si-based NVM, sensors, optoelectronic and logic devices2. However, integration of such materials onto Si is a very challenging task due to the possibility of cross interdiffusion at high temperature. Ferroelectric integration on closely lattice mismatched NdGaO3 or SrTiO3 substrates is an alternative approach towards fabrication of electronic devices, however, these substrates cannot be embedded into complementary metal-oxide-semiconductor (CMOS) systems for further device processing since current CMOS processing technologies are based on low-cost, large area Si5. Many researchers have attempted to implement the ferroelectric materials onto Si, but direct integration results in cross-diffusion that creates defect states and degrades the electrical transport properties3,4,6,7,8,9,10,11,12,13. Moreover, an interfacial reaction between the ferroelectric layer and the Si can provide poor charge retention property which ultimately hinders the device performance. To alleviate these problems, a high-k barrier layer was introduced by several researchers between the ferroelectric and the Si substrate3,4,6,7,8,9,10,11,12,13. The limitations of this approach are the presence of depolarization field across the ferroelectric layer and the large voltage drop across the oxide layer, which results in a poor device performance and also increases the device operation voltage13. The depolarization voltage implies polarization induced by an external field opposing the applied field and it could seriously affect the retention property of the NVM devices. In addition, the presence of a depolarization field can also affect the orientation of ferroelectric domains which may suppress the ferroelectric switching2. It is known that the performance of such NVM devices strongly depends on the switching of the ferroelectric polarization, since it can create high memory densities, as well as improve the retention properties2,14. The switching of ferroelectric domains, through nucleation and growth, occurs in presence of an external bias. In ferroelectric material, mechanical strain and depolarization field have been found to have a large impact on the formation of polarization domains. When one wants to integrate ferroelectric thin films with Si, the domain formation is controlled by the lattice mismatch between the thin films and the substrate and interfacial defects could also arise during processing steps15.
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